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MC74HC05A Hex Inverter with Open Drain Outputs
The MC74HC05A contains six inverters with open drain outputs. The MC74HC05A is identical to the MC74HC04A, except for the open drain outputs. The outputs can be connected to other open drain outputs to implement active LOW wired-OR or active High wired-AND logic functions. The open drain outputs require pull-up resistors to perform correctly.
Features http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 N SUFFIX CASE 646 1 14 14 1 SOIC-14 D SUFFIX CASE 751A 1 HC05AG AWLYWW
* Output Drive Capability: 10 LSTTL Loads with Suitable Pull-up * * * * * * *
Resistor Outputs Directly Interface to CMOS, NMOS and TTL High Noise Immunity Characteristic of CMOS Devices Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 36 FETs or 9 Equivalent Gates These are Pb-Free Devices
LOGIC DIAGRAM
A1 1 2 Y1 14 1 A2 3 4 Y2 14 1
MC74HC05AN AWLYYWWG
14 TSSOP-14 DT SUFFIX CASE 948G 1 HC 05 ALYWG G
A3
5
6
Y3 Y=A
A4
9
8
Y4
A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
A5
11
10
Y5
A6
13
12
Y6
FUNCTION TABLE
Inputs Outputs Y H L
Pinout: 14-Lead Packages (Top View)
VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8
A L H
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
1 A1
2 Y1
3 A2
4 Y2
5 A3
6 Y3
7 GND
(c) Semiconductor Components Industries, LLC, 2009
November, 2009 - Rev. 0
1
Publication Order Number: MC74HC05A/D
MC74HC05A
MAXIMUM RATINGS
Symbol VCC Vin Vout Iin Iout ICC PD DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package Parameter DC Supply Voltage (Referenced to GND) Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 - 65 to + 150 260 Unit V V V mA mA mA mW
Tstg TL
Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
_C _C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Derating - Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 - 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns
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MC74HC05A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage Condition Vout = 0.1V or VCC -0.1V |Iout| 20mA Vout = 0.1V or VCC - 0.1V |Iout| 20mA Vout = 0.1V or VCC - 0.1V |Iout| 20mA Vin = VIH or VIL Iin ICC IOZ Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum Three-State Leakage Current Vin = VCC or GND Vin = VCC or GND Iout = 0mA Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND |Iout| 4.0mA |Iout| 5.2mA VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 Guaranteed Limit -55 to 25C 1.50 3.15 4.20 0.50 1.35 1.80 0.1 0.1 0.1 0.26 0.26 0.1 1.0 0.5 85C 1.50 3.15 4.20 0.50 1.35 1.80 0.1 0.1 0.1 0.33 0.33 1.0 10 5.0 125C 1.50 3.15 4.20 0.50 1.35 1.80 0.1 0.1 0.1 0.40 0.40 1.0 40 10 mA mA mA Unit V
VIL
Maximum Low-Level Input Voltage
V
VOL
Maximum Low-Level Output Voltage
V
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol tPLZ, tPZL tTHL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 90 18 15 75 15 13 10 10 85C 115 23 20 95 19 16 10 10 125C 135 27 23 110 22 19 10 10 Unit ns
ns
Cin Cout
pF pF
Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer)* 4.0 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC .
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MC74HC05A
VCC tr INPUT A 90% 50% 10% tPZL OUTPUT Y 90% 50% 10% tTHL tPLZ tf VCC GND HIGH IMPEDANCE 10% VOL *Includes all probe and jig capacitance DEVICE UNDER TEST
1kW OUTPUT
Rpd TEST POINT CL*
Figure 1. Switching Waveforms
25 TYPICAL T=25C 20 I D, SINK CURRENT (mA) T=25C 15 T=85C 10 T=125C EXPECTED MINIMUM* 5 VCC=5V
Figure 2. Test Circuit
0 0 1 2 3 4 VO, OUTPUT VOLTAGE (VOLTS) 5
*The expected minimum curves are not guarantees, but are design aids.
Figure 3. Open-Drain Output Characteristics
ORDERING INFORMATION
Device MC74HC05ANG MC74HC05ADG MC74HC05ADR2G MC74HC05ADTR2G MC74HC05AFG MC74HC05AFELG Package PDIP-14 (Pb-Free) SOIC-14 (Pb-Free) SOIC-14 (Pb-Free) TSSOP-14* SOEIAJ-14 (Pb-Free) SOEIAJ-14 (Pb-Free) 50 / Rail 2000 / Tape & Reel Shipping 25 / Rail 55 / Rail
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC05A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC74HC05A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EEE CCC EEE CCC CCC
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
K1
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC05A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74HC05A/D

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